Currently all PLLS, except the all-digitally-implemented PLLS, utilise a VCO to provide the clocking means. A VCO is employed for example, for this purpose in the design of a magnetic recording channel.
A major problem in the design of PLLs is ensuring a very tight tolerance for the free-running frequency of the VCO. To achieve this, temperature compensation techniques are often incorporated into the design of the VCO circuitry. However, since the variations in process parameters (such as oxide thickness, threshold voltage, etc.) are statistically independent of each other; the effect on the circuit cannot be fully overcome using design techniques. The VCO free-running frequency tolerance be very tight and not vary more than 1%-2%.
Heretofore, the chip-to-chip variation in VCO free-running frequency was resolved by physically modifying the PLL chip by (1) using a laser trim technique involving trimming resistors or capacitors which are on the module substrate and connected to the VCO circuit inside the chip; or (2) a high current zapping technique to blow out resistors on the chip at the wafer level; or (3) using digital-to-analog (D/A) converters to convert the variations into bias voltage to be applied to the VCO.
The general state of the prior art with respect to solving the problem of process tolerance is illustrated with reference to the following patent:
U.S. Pat. No. 4,929,918 describes a circuit for setting the free-running frequency of a VCO which forms part of a PLL, using D/A converters (DAC). At system power on, the PLL is automatically disabled and a DAC in the PLL is set to a value corresponding substantially to the center of a pre selected lock range. A frequency-locked loop (FLL), interconnected to the PLL and which includes a second DAC operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count, whereupon the VCO will be set at its free-running frequency.
All the previous cited techniques are expensive and time consuming. The high current zapping technique is unreliable for the tight tolerances required for a VCO.
The DAC components are not suitable for low gain VCO, and particularly not suitable for high operating frequencies (over 100 Mhz). Moreover, the DAC components are hardware expensive.
None of the cited techniques and references teach a system for setting the free-running frequency of a VCO which is fully digital. Moreover, none of these references suggest a system which operates on a high operating frequency (above 100 MHz) and which is particularly suitable for low gain VCO.
Accordingly, it would be desirable to provide an apparatus and associated method which eliminates the aforementioned problems.